It is known to use a plurality of lines in a bus to transmit a plurality of data bits simultaneously, thereby achieving high data transmission rates. However, certain devices, are designed to transmit and receive data in a serial format, thereby sacrificing data rate to minimize the number of interface lines.
Two prior art serial communication interface configurations are known and commonly implemented with A/D converters. These two types of configurations are known as the nonregistered configuration and the registered configuration. FIG. 1b illustrates an example of a timing diagram corresponding to a nonregistered type serial interface shown in FIG. 1a, and FIG. 2b shows a timing diagram corresponding to a registered type serial interface of FIG. 2a. In both configurations, conversion begins when the Not Chip Select ("/CS") signal transitions from a logic "one" (high) to a logic "zero" (low). During the first five system clock cycles ("CLK"), the first five data input ("DI") bits provided are latched. These include the start bit, a single-ended or differential mode bit, a sign bit, and two bits for channel selection. After a predefined acquisition period T.sub.acq following the falling edge of the fifth CLK cycle, Successive Approximation Registers ("SARS") signal transitions from low to high, indicating the beginning of data conversion, i.e. such as A/D conversion.
FIG. 1b shows a prior art nonregistered format serial communication interface process which invokes conversion of DI bits upon detecting the signal state of /CS signal as being asserted, i.e. low, and Successive Approximation Register Signal (SARS) as being high. Prior art nonregistered configuration serial interfaces output converted data output ("DO") bits during the data conversion. Converted data DO are therefore not stored internally, but are provided serially at a data output signal port (not shown) as each successive DO bit becomes available. As shown in FIG. 1b converted data bit DO of nonregistered type serial interface is available upon the serial interface detecting the rising edge of SARS, with the most significant bit (MSB) DO bit provided first at the output port. However, the nonregistered approach as shown in FIG. 1b is not always practical beyond 12 bits due to induced noise from the output buffer.
FIG. 2b illustrates a registered configuration serial interface. In the registered format, the converted bits are available at the data output only after the entire conversion process has been completed. During conversion, converted data, DO bits, are temporarily stored in an internal register until conversion of data DI is completed. When SARS transitions from high to low, the falling edge of SARS is used to indicate the end of data conversion. Upon the next rising edge of CLK, DO bits are provided to the data output port (not shown) with the Least Significant Bit (LSB) first. Thus, in the registered type serial interface, the LSB of DO is first routed to the data output signal port followed by the subsequent bits.
In both the registered and the nonregistered configuration the system microprocessor must continuously monitor the status of the conversion, i.e. the changing state of SARS to detect the falling edge of SARS, which is additional overhead for a system microprocessor. Moreover, during this conversion process, /CS must be low for the selected chip to remain active. Since /CS is asserted during a conversion, other chips which share the same input or output ("I/O") signal lines, such as SARS, DO, and DI, cannot be selected during the conversion process. Thus, prior art registered or nonregistered format serial interfaces do not efficiently accommodate systems having multiple A/D converters, or multiple I/O devices.
Another prior art serial interface uses a modified registered output configuration such as the registered type A/D serial interface ADC0819 ("the ADC0819") provided by National Semiconductor Corporation. The modified registered serial interface of the ADC0819 implements two clock signals for serial interface operation. The first clock (CLK1) is a system operation clock, and the second clock (CLK2) is an I/O interfacing clock. FIGS. 3 and 4 illustrate two alternative modes of operation available with the modified registered serial interface configurations provided by the ADC0819. FIG. 3 shows a first operation mode of ADC0819, where data conversion is invoked with the rising edge of /CS. Since no SARS is provided in the ADC0189, /CS remains high during data conversion. After data conversion is completed, and on the falling edge of /CS, converted data DO bits are provided at a data output port.
FIG. 4 shows a second operation mode of the modified registered output configuration provided by ADC0819. Clock signal CLK2 is used to control the output of converted data DO to the data output port. When the last converted data DO bit is transferred to an output data shift register, CLK2 is inhibited thereby preventing clocking out of DO. After a prescribed time (a minimum of 16 .mu.sec for the ADC0819), CLK2 is restarted and converted data DO is provided serially to the output port, The modified registered serial interface of ADC0819 not only requires an extra clock signal, but also requires additional overhead control circuitry.
Thus, with prior art registered type serial interface architecture, such as the one exemplified in FIG. 1b, microprocessor overhead exists to continuously monitor for the falling edge of SARS to detect the end of data conversion. Alternatively, in most applications of serial interfaces where data is not needed immediately after conversion, delays to providing the output data DO may be achieved by the modified registered type serial interface ADC0819 (FIGS. 3 and 4). However, such delayed output is achieved at a cost of requiring an additional clock signal. Moreover, inhibiting data output requires precise clock signal edge detection, which is cumbersome to implement and consumes system microprocessor overhead. Although the nonregistered configuration serial interface (shown in FIG. 2b) is faster than registered configuration, the nonregistered configuration serial interface is more sensitive to internal noise. Thus, there is a need for an efficient serial communication interface architecture that provides controllable delay to data output, while minimizing additional circuitry and system overhead.